Normally silicon chip microprocessors including a central processing unit CPU, a read only memory ROM, a random access memory RAM and an output-input interface I/O are formed on a single chip (one-chip microcomputer) and are arranged to operate on a 5 V power supply. However, recently a demand for a one-chip microprocessor which can be operated on batteries has developed. This requires that the supply on which the device is to be operated can be selectively reduced from 5 V to 3 V. This reduction induces a change in the generation of clock pulses which are used in connection with the operation of the CPU. When this change occurs however, improper operation is apt to occur.
Accordingly, it is required to be able to produce low speed clock pulses when this reduction in power occurs in a manner which renders it possible to maintain proper operation. It is additionally required to be able to provide low speed clock signals, when the power supply is reduced for the purpose of conserving electrical power, and/or in the event of a power blackout.
Moreover, it is desirable to be able to expand control over the reading and writing cycles when accessing an external low speed expansion memory.
In order to achieve the above it has been proposed to use two clock pulse generators--one for high speed pulse signals and one for low speed pulse signals. However, this arrangement is such that when one is in use the other is rendered redundant. Further, when switching from one to another, it often occurs that an asynchronism or misalignment occurs in the relationship between the pulses.